Research and development efforts are being made for reduction in minimum device dimension to increase the integration density of component elements fabricated on a single semiconductor substrate, and a multi-level wiring structure tends to be employed in a semiconductor device for the same purpose. For example, a static random access memory device has a memory cell arrangement formed by a flip-flop circuit, and the flip-flop circuit is usually provided with two load resistors coupled between a source of voltage and switching transistors arranged in a cross-coupled manner. It is preferable for the load resistors to have a large resistance for the sake of reduction in power consumption, so that thin and narrow polysilicon layers are formed as a second level of the multi-level wiring structure so as to provide the resistors of the flip-flop circuit. The resistors need to be supplied with an electric power, and an aluminum wiring layer is formed over the resistors as a third level of the multi-level wiring structure contacting through contact holes formed in an insulating film between the second and third levels. Namely, as shown in FIG. 1, the high resistive polysilicon layers 1 are formed over a semiconductor substrate 2 overlain by a first insulating film 3 of, for example, silicon dioxide, and a second insulating film 4 of silicon dioxide is deposited on the entire surface of the structure as shown in FIG. 1 of the drawings. Contact holes 5 are formed in the second insulating film 4 to partially expose the respective high resistive polysilicon layers 1, and, thereafter, aluminum is deposited on the second insulating film 4 to form contacts between the aluminum layer 6 and the polysilicon layers 1.
However, a problem is encountered in the fabrication process of the multi-level structure in over-etching of the insulating material. In detail, when the etching process is applied to the second insulating film 4 for formation of the contact holes 5, the etching gaseous mixture tends to pass through the thin polysilicon layers and continues to etch the first insulating film 3 to form cavities 7 underneath the polysilicon layers. This is because of the fact that the polysilicon layers 1 have a lot of grain boundaries through which the etching gaseous mixture flows. If the polysilicon layers 1 are small in thickness of about 1000 angstroms, the over-etching problem is serious, and there is a possibility to break the polysilicon layers. If the cavities are formed in the first insulating layer 3, the contacts between the aluminum layer and the polysilicon layers 1 are liable to be broken, which results in deterioration in production yield.